Japanese Patent Application No. 2000-163021, filed May 31, 2000, is hereby incorporated by reference in its entirety.
The present invention relates to a semiconductor device having an electrostatic protection circuit and a method of fabricating the same.
A major cause of an electrostatic breakdown phenomenon is silicon dissolution due to heat generated at a PN junction at the time of discharge or occurrence of contact spiking in which a metal of a metal electrode is diffused into a silicon substrate. Conventional countermeasures for static electricity have been carried out taking this point into consideration.
Accompanied by miniaturization of devices, in a miniaturization process with a design rule of 0.35 xcexcm or less, salicide transistors have been developed in order to effectively decrease the resistivity of source/drain diffusion layers by employing salicide technology in which a high-melting-point metal silicide layer is formed on the diffusion layers (Japanese Patent Applications Laid-open No. 7-273197, No. 7-106570, No. 7-94595, No. 5-136086, No. 3-234062, and the like).
The thickness of a gate oxide film, which is normally 135 Angstroms in a device with a supply voltage of 5 V, tends to be decreased as the supply voltage is decreased. In a 0.35 xcexcm process, the thickness of the gate oxide film is 70 Angstroms in a device with a supply voltage of 3.3 V, for example. In a 0.25 xcexcm process, the thickness of the gate oxide film is about 50 Angstroms in a device with a supply voltage of 2.5 V. This is a serious hindrance in designing electrostatic protection circuits.
When allowing an electrostatic charge injected from an input/output terminal to be discharged through a power supply terminal, in the case where a silicide layer is present on the junction of a discharge device (such as a MOS transistor) interposed between the input/output terminal and the power supply terminal, the discharge device breaks down at a very low applied voltage.
The cause of the breakdown estimated from delamination analysis results is the occurrence of local current concentration near a gate electrode, because a notch-shaped trace of current flowing near the gate electrode of the MOS transistor occurred.
As a reason why current concentration tends to occur locally, a decrease in the resistivity of the diffusion layers by using the salicide technology can be given. In the case of applying a reverse voltage to the N-type MOS transistor, a charge injected from a pad is injected into the diffusion layers from a contact on the drain, and causes avalanche breakdown (electron avalanche) to occur at the junction with a channel region. The charge flowing out into the substrate causes the potential difference necessary for allowing a diode forward current to be produced between a source potential (ground potential) and a substrate potential. This causes a bipolar transistor formed by drain-channel-source to be operated, whereby the current is discharged with the voltage being clamped.
The state of discharge is described below with reference to FIGS. 32 and 33. FIGS. 32 and 33 are plan views showing an N-type MOS transistor including a drain 10, contacts 12 formed on the drain 10, a gate 14, a source 16, and contacts 18 formed on the source 16.
In the case where a silicide layer is not formed on the diffusion layers, the current uniformly flows from the contacts 12 on the drain 10 toward the gate 14 without being concentrated in one spot due to high diffusion resistivity, as shown in FIG. 32.
On the contrary, in the case where a silicide layer is formed on the diffusion layers, when a hot spot 20 is formed as shown in FIG. 33, the current is concentrated from all the contacts 12 on the drain 10 in the hot spot 20. Therefore, current concentration tends to occur even if the applied voltage is low, thereby causing breakdown to occur.
Moreover, the silicide layer cannot be formed flat near the junction, so that the silicide in the shape of a projection is present at a junction edge. Current concentration tends to occur in this area therefore the hot spot tends to occur.
An electrostatic discharge (ESD) withstanding voltage is considered to be decreased for these two reasons in the case where the silicide layer is present on the junction of the discharge device.
Therefore, technology additionally including a protection step for partly removing the silicide layer on the discharge device has been developed (Japanese Patent Application Laid-open No. 2-271673 and the like).
However, the following two problems occur when employing the protection step.
One of the problems is that leakage may occur between the gate and the source/drain. In the protection step, an oxide film is formed over the entire surface of the substrate after forming the source/drain regions and is etched while allowing the area in which the silicide is not formed to remain. A side-wall insulating film which has already been formed on the side of the gate is also removed during the etching so that leakage easily occurs.
The other problem is that high-speed operation of the transistor cannot be expected. In a full salicide process in which the silicide layer is formed on both the gate electrode and the diffusion regions, it is impossible to employ a structure in which the silicide layer is formed on the gate electrode but is not formed near the drain junction. Therefore, preventing the silicide layer from being formed near the drain junction causes a region to be formed on the gate electrode in which the silicide layer is not formed. This results in a sheet resistance of the order of KQ so that the high-speed operation cannot be expected.
According to one aspect of the present invention, there is provided a semiconductor device comprising:
a semiconductor substrate;
a MOS transistor which is formed on the semiconductor substrate and includes a first diffusion region;
a first isolation region which isolates the MOS transistor from other MOS transistors on the semiconductor substrate;
a second isolation region formed between the MOS transistor and the first isolation region;
a silicide layer formed on a surface of the semiconductor substrate excluding the first and second isolation regions;
a second diffusion region which is formed in a region isolated by the second isolation region and makes up a lateral bipolar transistor together with a well in the semiconductor substrate; and
a third diffusion region which is formed at a deeper position of the first diffusion region near the second isolation region and makes up a Zener diode by the PN junction together with the first diffusion region of the MOS transistor.
Another aspect of the present invention provides a method of fabricating a semiconductor device comprising the steps of:
forming a first isolation region which isolates a MOS transistor to be formed on a semiconductor substrate from other MOS transistors;
forming a second isolation region between the first isolation region and a region in which the MOS transistor is to be formed;
forming a P-type well and an N-type well in the semiconductor substrate;
forming a first diffusion region of the MOS transistor in a part of the P-type and N-type wells near the boundary of the P-type and N-type wells of the semiconductor substrate;
forming a second diffusion region which make up a lateral bipolar transistor together with one of the P-type well and the N-type well of the semiconductor substrate in a region isolated by the second isolation region;
forming a third diffusion region which makes up a Zener diode by the PN junction together with the first diffusion region of the MOS transistor, in a region near the second isolation region and a deeper part of the first diffusion region; and
forming a silicide layer on a surface of the semiconductor substrate excluding the first and second isolation regions.
According to still another aspect of the present invention, there is provided a semiconductor device comprising:
a semiconductor substrate;
a MOS transistor which is formed on the semiconductor substrate and includes a first diffusion region;
a first isolation region which isolates the MOS transistor from other MOS transistors on the semiconductor substrate;
a second isolation region formed between the MOS transistor and the first isolation region;
a second diffusion region which is formed in a region isolated by the second isolation region and makes up a lateral bipolar transistor together with a well in the semiconductor substrate;
a third diffusion region which is formed between the second isolation region and the first diffusion region and near a surface of the semiconductor substrate and makes up a Zener diode by the PN junction together with the first diffusion region of the MOS transistor; and
a silicide layer formed on a surface of the semiconductor substrate excluding the first and second isolation regions and a region connecting the first and third diffusion regions.
A further aspect of the present invention provides a method of fabricating a semiconductor device comprising the steps of:
forming a first isolation region which isolates a MOS transistor to be formed on a semiconductor substrate from other MOS transistors;
forming a second isolation region between the first isolation region and a region in which the MOS transistor is to be formed;
forming a P-type well and an N-type well in the semiconductor substrate;
forming a first diffusion region of the MOS transistor in a part of the P-type well and the N-type well near the boundary of the P-type and N-type wells of the semiconductor substrate;
forming a second diffusion region which make up a lateral bipolar transistor together with one of the P-type well and the N-type well of the semiconductor substrate in a region isolated by the second isolation region;
forming a third diffusion region which makes up a Zener diode by the PN junction together with the first diffusion region of the MOS transistor, between the second isolation
region and the first diffusion region and near a surface of the semiconductor substrate and; and forming a silicide layer on a surface of the semiconductor substrate excluding the first